1. Field of Use
The present invention relates to field of electronic testing and, in particular, to the testing of printed circuit boards (PCBs). The invention more particularly relates to testing for proper connection to and from electronic devices mounted on a PCB.
2. Relevant Art
The benefits of being able to test for proper connection between the various devices mounted on PCBs has long been recognized as beneficial both in fault detection and diagnosis. That is, while testing the PCB as a functional unit is important in itself, there are advantages to separately testing the interconnects, especially in PCB designs in which the functionality is complex. Such designs are sometimes referred to as being comprised of random logic, because the challenge of testing differs from that of more straightforward designs, such as is the case with, for example, main memory units. In the latter type, the same or similar clusters of logical functions may exist in perhaps over a hundred instances. Additionally, these clusters of logical functions may be the same or similar to those functions which have existed in digital computers for decades and for which tests have been developed and perfected over time.
Various methods have been developed to address the testing challenges of interconnect testing. One such method is termed boundary scan, where a secondary layer of logic (test logic) is added to the primary layer of logic (functional logic) of each boundary scan device and controlled by extra connections to the device. IEEE Standard 1149.1 defines a method of boundary scan widely used in the industry. The IEEE Standard 1149.1 was developed as a refinement of an international industry effort termed “Joint Test Action Group” (JTAG). Presently, the term JTAG is also used to refer both to devices which are IEEE Standard 1149.1 compliant and devices which may be slightly lacking in compliance to the standard. The term IEEE 1149.1 will be used herein to include both classes of devices (i.e., completely compliant and mostly compliant).
IEEE 1149.1 devices incorporate three or four extra test input connections (TDI, TCK, TMS or TDI, TCK, TMS, TRST*, respectively) to control the internal device test logic. Such a device operates in either a functional mode or a test mode, depending on the signals received at those test input connections and upon the time interval since the device was powered up. That is, it is a norm that IEEE 1149.1 devices with only the three extra test inputs are designed to achieve a completely functional (non-test) state within a given interval after power up. It should be noted that the term “states of a device” as used herein refers to which logical layer is controlling the non-IEEE 1149.1 outputs of the device. That is, in the test state, the boundary scan layer controls most device outputs, whereas in the functional device state, the functional logic layer controls most device outputs. Exceptions are the single IEEE 1149.1 output connection (TDO), which is always controlled by the test logic, and certain other functional connections, such as analog connections, and power connections.
While the IEEE 1149.1 capability has been included on many complex devices, such as microprocessors and the like, many simple devices, such as separate groups of AND or OR gates, for example, are not available in IEEE 1149.1 versions. In the case of such simple devices, the added IEEE 1149.1 logic might be more complex than the functional logic of the device. Also, the simple logic paths that these devices provide between more complex devices are often easily testable by means of the IEEE 1149.1 circuitry extant in complex devices and automatic test pattern generation (ATPG) software commonly used to write IEEE 1149.1 test patterns. The decision not to include IEEE 1149.1 logic in a device is made by the device manufacturer, as a marketing choice. That is, the manufacturer decides whether or not the additional cost of an IEEE 1149.1 version of a device will be sufficiently welcomed in the market.
Memory devices have largely fallen into the category of devices which do not incorporate IEEE 1149.1 circuitry. Reasons for the manufacturer decisions not to include IEEE 1149.1 may be the extremely competitive nature of the memory device industry, the inherent propagation delay, however minor, of adding any circuitry to the functional connections and the PCB etching problems imposed by the IEEE 1149.1 interconnects. There may be other reasons, as well, including what may be possibly the main reason manufacturers do not include IEEE 1149.1 circuitry on most memory devices: the nature of main memory PCB designs incorporating those devices. In some key respects, the designs are very similar to those of the past and can be tested by test programs very similar to those developed over decades. These test programs generally have high fault detection and fault diagnosis capabilities. Hence, there is less to be gained by adding IEEE 1149.1 circuitry to memory devices in comparison to adding it to microprocessors, for example.
In memory device applications other than main memory applications, interconnect testing may be extremely difficult. That is, unless the memory device contains IEEE 1149.1 circuitry, its connection to one or more devices which do may not solve the test problem. For example, in a case where the memory device operation has timing requirements which cannot be met by boundary scan operations, such testing may be impossible. To address this problem, another standard has been proposed, IEEE Standard P1581 (hereinafter referred to as IEEE P1581). As with IEEE 1149.1, an IEEE P1581 device would have both a test mode and a functional mode. However, the circuitry used in the IEEE P1581 test mode would be much less complex than the circuitry required for IEEE 1149.1. The circuitry may be simple gates such as AND, NAND, OR, NOR, XOR and XNOR, connected between device inputs and outputs in predetermined patterns, although more complex logic functions, such as storage elements, are not precluded from use. These logic functions enable signals from IEEE 1149.1 circuitry in another device or devices to propagate through the memory device and stimulate inputs of the same or other IEEE 1149.1 devices. The use of simple gating in IEEE P1581 means there is a minimum of extra circuitry involved in the memory devices, although the economy of circuitry has little relative effect on the cost of device fabrication because of the small size of either type of test circuit (i.e., IEEE 1149.1 vs. IEEE P1581) in comparison to the functional circuitry of a memory of substantial size. The principal benefit of IEEE P1581 is that only one extra connection to the device is needed to select test mode or functional mode. In certain memory devices, there may even be one or more combinations of input signals which serve no functional purpose. In such instances, one or more such input signal combinations may be used to set or reset the test mode, obviating extra connections. Memory devices having such unused input signal combinations, however, are the exception rather than the rule. Therefore, incorporating an IEEE P1581 capability into a device will commonly require an otherwise unnecessary connection to the device. Even this single added connection will likely be perceived by suppliers as presenting a marketing disadvantage in main memory applications, which represents the largest market for many memory devices and where, as stated, the test advantage of IEEE P1581 is minimal because of the availability of adequate test methods which work well without the IEEE P1581 test circuitry.
Therefore, it is an objective of the present invention to provide a method of allowing a memory device to have dual operating modes (test and functional) which are achieved without extra device connections.
It is a further objective of the present invention that the stated mode selection be independent of input combinations which are unused during device functional operation.